FIG. 1 is a schematic cross-sectional view of a heterojunction bipolar transistor (HBT) of the prior art. N+ polysilicon emitter 10 sits atop base layer 11a of silicon-germanium. The actual area where it makes contact to the Si—Ge (i.e. the heterojunction) is restricted by the presence of insulating layers 18 and 19 of silicon nitride and silicon oxide respectively, the former having been used as a hard mask during manufacturing. The emitter pedestal is further protected by means of spacers 17 on its vertical sidewalls.
In order to be able to contact the base region, SiGe layer 11a has been laterally extended from both sides as layer 11b. The resistivity of 11a needs to be relatively high (to ensure efficient injection of electrons from the emitter) while the resistivity of 11b needs to be as low as possible in order to minimize the base resistance (which in turn controls the cutoff frequency of the device). During manufacturing, 11a and 11b are deposited as a single layer of relatively high resistivity. After formation of the emitter pedestal, the latter acts as a mask during implantation of acceptor ions (usually boron) into 11b whereby its resistivity is then substantially lowered.
Other features seen in FIG. 1 include N type silicon body 16 from whose upper surface N+ collector volume 12 extends downwards. Connection to collector 12 is made through N+ sinker 14 which is connected to 12 through buried N+ layer 13. Electrical isolation from other parts of the integrated circuit is achieved by means of dielectric-filled deep and shallow trenches 15.
There are several problems associated with the design seen in FIG. 1. In particular, when external base 11b is doped by ion implantation, implant damage occurs which leads to enhanced internal base diffusion. This, in turn, will enhance emitter junction diffusion, leading to an increase in emitter and base junction width which will degrade the speed of the device.
The present invention teaches how the device can be manufactured without the need to include the damaging ion implant step that is inherent to the prior art. This allows achievement of very shallow base and emitter junctions for the same thermal budget.
A routine search of the prior art was performed with the following references of interest being found:
In U.S. Pat. No. 6,169,007 B1, Pinter shows a HTB with an epi base. In U.S. Pat. No. 5,846,867, Gomi et al. disclose a method for a Si—Ge base in a HBT. Cho et al., in U.S. Pat. No. 5,897,359, show a method for a HBT while Kim shows a process for a transistor having an epi base in U.S. Pat. No. 6,060,365.